Add support of x86-64.
Most change was done in #ifdef TCC_TARGET_X86_64. So, nothing should be broken by this change. Summary of current status of x86-64 support: - produces x86-64 object files and executables. - the x86-64 code generator is based on x86's. -- for long long integers, we use 64bit registers instead of tcc's generic implementation. -- for float or double, we use SSE. SSE registers are not utilized well (we only use xmm0 and xmm1). -- for long double, we use x87 FPU. - passes make test. - passes ./libtcc_test. - can compile tcc.c. The compiled tcc can compile tcc.c, too. (there should be some bugs since the binary size of tcc2 and tcc3 is differ where tcc tcc.c -o tcc2 and tcc2 tcc.c -o tcc3) - can compile links browser. It seems working. - not tested well. I tested this work only on my linux box with few programs. - calling convention of long-double-integer or struct is not exactly the same as GCC's x86-64 ABI. - implementation of tcc -run is naive (tcc -run tcctest.c works, but tcc -run tcc.c doesn't work). Relocating 64bit addresses seems to be not as simple as 32bit environments. - shared object support isn't unimplemented - no bounds checker support - some builtin functions such as __divdi3 aren't supported
This commit is contained in:
Shinichiro Hamaji
committed by
grischka
grischka
parent
fb0ac27691
commit
0a9873aa22
138
tcc.c
138
tcc.c
@ -79,15 +79,16 @@
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//#define TCC_TARGET_I386 /* i386 code generator */
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//#define TCC_TARGET_ARM /* ARMv4 code generator */
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//#define TCC_TARGET_C67 /* TMS320C67xx code generator */
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//#define TCC_TARGET_X86_64 /* x86-64 code generator */
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/* default target is I386 */
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#if !defined(TCC_TARGET_I386) && !defined(TCC_TARGET_ARM) && \
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!defined(TCC_TARGET_C67)
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!defined(TCC_TARGET_C67) && !defined(TCC_TARGET_X86_64)
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#define TCC_TARGET_I386
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#endif
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#if !defined(_WIN32) && !defined(TCC_UCLIBC) && !defined(TCC_TARGET_ARM) && \
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!defined(TCC_TARGET_C67)
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!defined(TCC_TARGET_C67) && !defined(TCC_TARGET_X86_64)
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#define CONFIG_TCC_BCHECK /* enable bound checking code */
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#endif
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@ -96,7 +97,8 @@
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#endif
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/* define it to include assembler support */
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#if !defined(TCC_TARGET_ARM) && !defined(TCC_TARGET_C67)
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#if !defined(TCC_TARGET_ARM) && !defined(TCC_TARGET_C67) && \
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!defined(TCC_TARGET_X86_64)
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#define CONFIG_TCC_ASM
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#endif
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@ -531,6 +533,12 @@ struct TCCState {
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/* output file for preprocessing */
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FILE *outfile;
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#ifdef TCC_TARGET_X86_64
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/* buffer to store jump tables */
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char *jmp_table;
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int jmp_table_num;
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#endif
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};
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/* The current value can be: */
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@ -938,6 +946,10 @@ static inline int is_float(int t)
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#include "c67-gen.c"
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#endif
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#ifdef TCC_TARGET_X86_64
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#include "x86_64-gen.c"
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#endif
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#ifdef CONFIG_TCC_STATIC
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#define RTLD_LAZY 0x001
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@ -4769,26 +4781,33 @@ void save_reg(int r)
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r = p->r & VT_VALMASK;
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/* store register in the stack */
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type = &p->type;
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#ifndef TCC_TARGET_X86_64
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if ((p->r & VT_LVAL) ||
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(!is_float(type->t) && (type->t & VT_BTYPE) != VT_LLONG))
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type = &int_type;
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#else
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if (p->r & VT_LVAL)
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type = &char_pointer_type;
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#endif
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size = type_size(type, &align);
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loc = (loc - size) & -align;
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sv.type.t = type->t;
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sv.r = VT_LOCAL | VT_LVAL;
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sv.c.ul = loc;
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store(r, &sv);
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#ifdef TCC_TARGET_I386
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#if defined(TCC_TARGET_I386) || defined(TCC_TARGET_X86_64)
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/* x86 specific: need to pop fp register ST0 if saved */
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if (r == TREG_ST0) {
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o(0xd9dd); /* fstp %st(1) */
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}
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#endif
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#ifndef TCC_TARGET_X86_64
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/* special long long case */
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if ((type->t & VT_BTYPE) == VT_LLONG) {
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sv.c.ul += 4;
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store(p->r2, &sv);
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}
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#endif
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l = loc;
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saved = 1;
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}
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@ -4939,8 +4958,7 @@ void gbound(void)
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register value (such as structures). */
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int gv(int rc)
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{
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int r, r2, rc2, bit_pos, bit_size, size, align, i;
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unsigned long long ll;
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int r, rc2, bit_pos, bit_size, size, align, i;
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/* NOTE: get_reg can modify vstack[] */
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if (vtop->type.t & VT_BITFIELD) {
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@ -5019,7 +5037,10 @@ int gv(int rc)
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((vtop->type.t & VT_BTYPE) == VT_LLONG &&
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!(reg_classes[vtop->r2] & rc2))) {
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r = get_reg(rc);
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#ifndef TCC_TARGET_X86_64
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if ((vtop->type.t & VT_BTYPE) == VT_LLONG) {
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int r2;
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unsigned long long ll;
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/* two register type load : expand to two words
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temporarily */
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if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
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@ -5059,7 +5080,9 @@ int gv(int rc)
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vpop();
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/* write second register */
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vtop->r2 = r2;
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} else if ((vtop->r & VT_LVAL) && !is_float(vtop->type.t)) {
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} else
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#endif
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if ((vtop->r & VT_LVAL) && !is_float(vtop->type.t)) {
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int t1, t;
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/* lvalue of scalar type : need to use lvalue type
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because of possible cast */
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@ -5224,7 +5247,7 @@ void vpop(void)
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{
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int v;
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v = vtop->r & VT_VALMASK;
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#ifdef TCC_TARGET_I386
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#if defined(TCC_TARGET_I386) || defined(TCC_TARGET_X86_64)
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/* for x86, we need to pop the FP stack */
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if (v == TREG_ST0 && !nocode_wanted) {
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o(0xd9dd); /* fstp %st(1) */
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@ -5265,6 +5288,11 @@ void gv_dup(void)
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sv.type.t = VT_INT;
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if (is_float(t)) {
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rc = RC_FLOAT;
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#ifdef TCC_TARGET_X86_64
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if ((t & VT_BTYPE) == VT_LDOUBLE) {
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rc = RC_ST0;
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}
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#endif
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sv.type.t = t;
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}
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r = gv(rc);
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@ -5278,6 +5306,7 @@ void gv_dup(void)
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}
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}
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#ifndef TCC_TARGET_X86_64
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/* generate CPU independent (unsigned) long long operations */
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void gen_opl(int op)
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{
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@ -5512,6 +5541,7 @@ void gen_opl(int op)
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break;
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}
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}
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#endif
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/* handle integer constant optimizations and various machine
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independent opt */
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@ -5790,7 +5820,11 @@ void gen_op(int op)
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if (op >= TOK_ULT && op <= TOK_LOR) {
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check_comparison_pointer_types(vtop - 1, vtop, op);
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/* pointers are handled are unsigned */
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#ifdef TCC_TARGET_X86_64
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t = VT_LLONG | VT_UNSIGNED;
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#else
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t = VT_INT | VT_UNSIGNED;
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#endif
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goto std_op;
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}
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/* if both pointers, then it must be the '-' op */
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@ -5802,7 +5836,11 @@ void gen_op(int op)
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u = pointed_size(&vtop[-1].type);
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gen_opic(op);
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/* set to integer type */
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#ifdef TCC_TARGET_X86_64
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vtop->type.t = VT_LLONG;
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#else
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vtop->type.t = VT_INT;
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#endif
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vpushi(u);
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gen_op(TOK_PDIV);
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} else {
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@ -5815,8 +5853,18 @@ void gen_op(int op)
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swap(&t1, &t2);
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}
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type1 = vtop[-1].type;
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#ifdef TCC_TARGET_X86_64
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{
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CValue cval;
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CType ctype;
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ctype.t = VT_LLONG;
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cval.ull = pointed_size(&vtop[-1].type);
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vsetc(&ctype, VT_CONST, &cval);
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}
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#else
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/* XXX: cast to int ? (long long case) */
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vpushi(pointed_size(&vtop[-1].type));
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#endif
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gen_op('*');
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#ifdef CONFIG_TCC_BCHECK
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/* if evaluating constant expression, no code should be
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@ -6099,6 +6147,7 @@ static void gen_cast(CType *type)
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} else if ((dbt & VT_BTYPE) == VT_LLONG) {
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if ((sbt & VT_BTYPE) != VT_LLONG) {
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/* scalar to long long */
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#ifndef TCC_TARGET_X86_64
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/* machine independent conversion */
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gv(RC_INT);
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/* generate high word */
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@ -6113,6 +6162,14 @@ static void gen_cast(CType *type)
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/* patch second register */
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vtop[-1].r2 = vtop->r;
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vpop();
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#else
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int r = gv(RC_INT);
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if (sbt != (VT_INT | VT_UNSIGNED)) {
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/* x86_64 specific: movslq */
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o(0x6348);
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o(0xc0 + (REG_VALUE(r) << 3) + REG_VALUE(r));
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}
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#endif
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}
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} else if (dbt == VT_BOOL) {
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/* scalar to bool */
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@ -6571,20 +6628,31 @@ void vstore(void)
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#endif
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if (!nocode_wanted) {
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rc = RC_INT;
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if (is_float(ft))
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if (is_float(ft)) {
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rc = RC_FLOAT;
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#ifdef TCC_TARGET_X86_64
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if ((ft & VT_BTYPE) == VT_LDOUBLE) {
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rc = RC_ST0;
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}
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#endif
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}
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r = gv(rc); /* generate value */
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/* if lvalue was saved on stack, must read it */
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if ((vtop[-1].r & VT_VALMASK) == VT_LLOCAL) {
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SValue sv;
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t = get_reg(RC_INT);
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#ifdef TCC_TARGET_X86_64
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sv.type.t = VT_PTR;
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#else
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sv.type.t = VT_INT;
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#endif
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sv.r = VT_LOCAL | VT_LVAL;
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sv.c.ul = vtop[-1].c.ul;
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load(t, &sv);
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vtop[-1].r = t | VT_LVAL;
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}
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store(r, vtop - 1);
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#ifndef TCC_TARGET_X86_64
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/* two word case handling : store second register at word + 4 */
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if ((ft & VT_BTYPE) == VT_LLONG) {
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vswap();
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@ -6598,6 +6666,7 @@ void vstore(void)
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/* XXX: it works because r2 is spilled last ! */
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store(vtop->r2, vtop - 1);
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}
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#endif
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}
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vswap();
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vtop--; /* NOT vpop() because on x86 it would flush the fp stack */
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@ -7107,7 +7176,11 @@ the_end:
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/* long is never used as type */
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if ((t & VT_BTYPE) == VT_LONG)
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#ifndef TCC_TARGET_X86_64
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t = (t & ~VT_BTYPE) | VT_INT;
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#else
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t = (t & ~VT_BTYPE) | VT_LLONG;
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#endif
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type->t = t;
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return type_found;
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}
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@ -8044,8 +8117,14 @@ static void expr_eq(void)
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if (vtop != vstack) {
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/* needed to avoid having different registers saved in
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each branch */
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if (is_float(vtop->type.t))
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if (is_float(vtop->type.t)) {
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rc = RC_FLOAT;
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#ifdef TCC_TARGET_X86_64
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if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
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rc = RC_ST0;
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}
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#endif
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}
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else
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rc = RC_INT;
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gv(rc);
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@ -8115,6 +8194,11 @@ static void expr_eq(void)
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rc = RC_INT;
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if (is_float(type.t)) {
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rc = RC_FLOAT;
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#ifdef TCC_TARGET_X86_64
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if ((type.t & VT_BTYPE) == VT_LDOUBLE) {
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rc = RC_ST0;
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}
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#endif
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} else if ((type.t & VT_BTYPE) == VT_LLONG) {
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/* for long longs, we use fixed registers to avoid having
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to handle a complicated move */
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@ -9982,6 +10066,30 @@ static int rt_get_caller_pc(unsigned long *paddr,
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return 0;
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}
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}
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#elif defined(__x86_64__)
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/* return the PC at frame level 'level'. Return non zero if not found */
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static int rt_get_caller_pc(unsigned long *paddr,
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ucontext_t *uc, int level)
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{
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unsigned long fp;
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int i;
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if (level == 0) {
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/* XXX: only support linux */
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*paddr = uc->uc_mcontext.gregs[REG_RIP];
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return 0;
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} else {
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fp = uc->uc_mcontext.gregs[REG_RBP];
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for(i=1;i<level;i++) {
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/* XXX: check address validity with program info */
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if (fp <= 0x1000 || fp >= 0xc0000000)
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return -1;
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fp = ((unsigned long *)fp)[0];
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}
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*paddr = ((unsigned long *)fp)[1];
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return 0;
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}
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}
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#else
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#warning add arch specific rt_get_caller_pc()
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@ -10235,6 +10343,9 @@ TCCState *tcc_new(void)
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#if defined(TCC_TARGET_I386)
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tcc_define_symbol(s, "__i386__", NULL);
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#endif
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#if defined(TCC_TARGET_X86_64)
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tcc_define_symbol(s, "__x86_64__", NULL);
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#endif
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#if defined(TCC_TARGET_ARM)
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tcc_define_symbol(s, "__ARM_ARCH_4__", NULL);
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tcc_define_symbol(s, "__arm_elf__", NULL);
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@ -10301,6 +10412,10 @@ TCCState *tcc_new(void)
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/* XXX: currently the PE linker is not ready to support that */
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s->leading_underscore = 1;
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#endif
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#ifdef TCC_TARGET_X86_64
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s->jmp_table = NULL;
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#endif
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return s;
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}
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@ -10336,6 +10451,9 @@ void tcc_delete(TCCState *s1)
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dynarray_reset(&s1->include_paths, &s1->nb_include_paths);
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dynarray_reset(&s1->sysinclude_paths, &s1->nb_sysinclude_paths);
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#ifdef TCC_TARGET_X86_64
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tcc_free(s1->jmp_table);
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#endif
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tcc_free(s1);
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}
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